In conventional SoC designs, it is advantageous to incorporate floor planning to integrate designs in a way that is optimal for considerations such as power, performance and area. Floor planning refers to designing a floor plan for an integrated circuit, such as an application specific integrated circuit (ASIC). The floor plan provides a physical description of the layout of the integrated circuit. A conventional floor plan specifies, for example, physical placement of functional blocks (referred to as “macros”) in the integrated circuit and communication channels between the blocks. An integrated circuit may also be referred to as a “chip” and is typically made of semiconductor material.
A macro may be any functional block, such as any processing unit. For example, macro may be a central processing unit (CPU), modem, graphics processing unit, camera module, memory, and so forth. A macro may also include one or more (sub) macros that are within the macro.
In addition to physical descriptions of the integrated circuit, logical descriptions of the integrated circuit are also used in floor planning. Logical descriptions of the integrated circuit are provided by a hierarchical netlist that describes the interconnection of the macros, the logic cells within the macros and the logic cell terminals/ports. The number of logical connections provided in the netlist defines the number of physical connections such as interconnects and wires that are used to accommodate the logical connections. Each connection between the macros may also be referred to as a “net.”
The structure of the integrated circuit provides for nets that extend across a channel spacing that is positioned between the macros. The channel spacing between the macros has a defined width, that is a distance between the macros, and that may be referred to as a channel spacing width. A channel spacing width may be measured across any axis. For example, a channel spacing width may be measured along a horizontal axis, a vertical axis, a vertical axis and a horizontal axis, and so forth. The channel spacing width determines the number of nets that can be accommodated between the macros. In general, a greater channel spacing width may accommodate a larger number of nets.
Conventional integrated circuit design includes designing the channel spacing between macros to have a width that accommodates the largest number of nets used between the macros. For example, if there are a first set of nets and a second set of nets between a first macro and a second macro, the channel spacing is designed to have a width that accommodates the larger of the first set of nets and the second set of nets. Accordingly, while the channel spacing width is sufficient to accommodate the larger set, the channel spacing width is oversized with regard to the smaller set. The oversized space is wasted space that may negatively result in increasing the area of the integrated circuit. Thus, there is a need in the art for an improved system and method of floor planning.